Semiconductor-on-insulator (SOI) technology is becoming increasingly important in semiconductor processing. A SOI substrate structure typically contains a buried insulator layer, which functions to electrically isolate an ultra-thin semiconductor device layer from a base semiconductor substrate. Active devices, such as transistors, with fully depleted channel regions are typically formed in the ultra-thin semiconductor device layer of the SOI substrate.
Such devices (i.e., fully depleted SOI devices) offer many advantages over their bulk or partially depleted counterparts, including, but not limited to: lower junction capacitance (especially lower sidewall junction capacitance in comparison with partially depleted SOI devices), better off-current control (i.e., lower leakage current), improved roll-off characteristics and sub-threshold swing.
However, one disadvantage of the fully depleted SOI devices is that they typically have higher series resistance due to the limited junction depth in the ultra-thin semiconductor device layer. Silicidation of the ultra-thin semiconductor device layer also presents a problem due to the limited amount of silicon available in the ultra-thin semiconductor device layer for silicidation. Therefore, raised source and drain structures are typically employed in ultra-thin SOI devices, which increases the manufacturing costs as well as the defect density of the SOI devices. Moreover, some major stress methods (such as embedded SiGe or SiC) that have been recently developed for stress engineering may not be compatible with ultra-thin SOI configurations due to the limited junction depth.
Further, because the ultra-thin semiconductor device layer is completely isolated from the base semiconductor substrate without any body contact, a charge can build up in the semiconductor device layer, which in turn leads to undesirable self-heating of the SOI devices and deleterious floating body effects that adversely impact the device performance.
There is therefore a need for improved SOI substrates and SOI devices with reduced floating body effects and reduced contact resistance, without compromising the advantages associated with the ultra-thin semiconductor device layer. There is also a need for a simple and effective method of fabricating the improved SOI substrates and SOI devices at reduced costs with fewer defects.